Optimization of Communication Cost within Processor Arrays Caused by I/O

S. Siegel and R. Merker (Germany)

Keywords

Processor Array, Input/Output, Interconnection, Partition ing, Integer Linear Programming

Abstract

Fine grain parallel architectures such as processor arrays (PAs) play an important role in the acceleration of applica tions which demand high processing capabilities. Methods for the mapping of compute-intensive algorithms to PAs of ten neglect an efficient routing of input and output (I/O). We formulate an integer linear program (ILP) with the objective to minimize the cost of channels and regis ters within the PA which are required to route the I/O. This optimization problem is integrated in our framework for the design of PAs. There we use partitioning to map algorithms to PAs. I/O is caused by the algorithm itself and in partition ing by the intermediate data because of the sequential ex ecution of the partitions. The ILP for the routing of the I/O can be combined with an optimization problem which considers the efficient routing of the data dependencies of the algorithm within the PA. We demonstrate the combined approach on the edge detection algorithm.

Important Links:



Go Back