Circuit Design of an On-Chip Learning Neural Network

C. Lu, B. Shi, and L. Chen (PRC)

Keywords

Neural networks, On-chip learning, Analog circuit, Expandable

Abstract

An on-chip BP learning neural network chip with 8 neuron and 64-synapse is designed. It is expandable. Large-scale neural network with arbitrary layers can be constructed by connecting unit chips. A novel neuron circuit with programmable parameters is proposed. It generates not only the sigmoid function but also its derivative. The neuron has a push-pull output stage to gain strong driving ability in both charge and discharge processes, which is very important in heavy load situations. An improved Gilbert multiplier is also proposed. It has one end current output and precise zero point. The learning system itself can be used as a refresh tool to keep the weight value right. Simulation results show that it can accomplish on-chip BP learning. The unit chip is now under fabrication by a standard 0.6-┬Ám CMOS technology. Measurements can be done in a near future.

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