A Systolic Architecture of VLSI Implementation of Dynamic Time Warping for Speech Recognition

H. Jeong and Y. Kim (Korea)


Speech Recognition, DTW(Dynamic Time Warping), Filter Bank, FPGA(Field-Programmable Gate Arrays)


Recently, the Field-Programmable Gate Arrays(FPGA) re alization of speech recognition has been attracting a grow ing intereat. However, the existing speech recognition ar chitectures are more often than not based upon the soft ware and thus not suitable for direct implementation on hardware. In this paper, we present an architecture for word recognition that can be efficiently implemented with FPGA. The architecture consists of a newly derived dy namic time warping(DTW) that use only bit additions and shift operations. One advantage of this architecture is the spatial efficiency, which accommodates more words for a given limited space. Another advantage is the absence of multipliers, which increases computational speed by reduc ing propagation delays. The architecture detects the begin ning and end points of the word and finds the best match among the registered words. The simulation results show the competence of the temporal and spatial efficiency as well as the recognition rate in noisy environments.

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